Semiconductor manufacturers print die as close to the wafer edge as possible to maximize the number of devices per wafer. However, die near the wafer edge typically show the lowest yield. To address edge-yield issues, semiconductor manufacturers need to control where the edge of each film lands, such as on the planar front surface of the wafer or past the planar surface into the sloped bevel. Semiconductor manufacturers also need to match the perimeter of each film to those of films deposited before and after it during device processing.
Current inspection and metrology tools are used for process control, such as for inspecting epitaxial wafers, inspecting and measuring photoresist edge bead removal (EBR), or inspecting z-cut height of a film at a wafer edge. These current inspection and metrology tools detect a signal and generate a phase image of a sample. However, per hardware construction and alignment procedures, there is no clear physical mean for these signals. It can be problematic to interpret the signal or link it to sample parameters, which has limited further development. Furthermore, since the collection efficiency of optics can vary from wafer to wafer at a wafer edge, from a metrology requirement point of view only one quantity can be deduced from the raw signals, which limits the amount of information that can be extracted from the signals.
Therefore, what is needed is a new system and method for wafer inspection and metrology.